This invention pertains generally to memory devices for high speed digital computers and the like and, more particularly, to a bipolar transistor memory cell and method for use in a random access memory.
Three types of random access memory cells are commonly utilized to provide high speed operation with bipolar peripheral circuits. These include emitter coupled SCR (silicon controlled rectifier) cells, switched collector load cells, and 6 transistor CMOS cells.
A standard SCR memory cell is illustrated in FIG. 1. This cell has a pair of cross coupled SCR circuits 11, 12 which hold the state of the cell Cells of this type are commonly employed in memory arrays in which a number of similar cells are organized by rows representing data words and columns representing individual bits within the words, with the left and right bitlines for a column being connected directly to the emitters of the transistors in the SCR circuits.
The standard SCR memory cell has certain limitations and disadvantages. It requires a deep base implant, which requires a relatively complex fabrication process. Inverse leakage reduces the standby current in the cell and causes an unbalancing of bitline currents, which results in soft error sensitivity, low yield and slower access times.
The invention provides a new and improved bipolar transistor memory cell and method in which a pair of state elements are cross coupled so that they assume opposite states in accordance with signals applied thereto, a pair of bipolar pass transistors are connected to respective ones of the state elements for applying signals to the state elements, and current flow through the pass transistors is monitored to determine the states of the state elements.